The wide acceptance and current popularity of data transmission is evidenced by the amount of commercially available digital peripheral equipment which is connectable to computer processors, or the like. By and large, data processing systems required intercommunication between extremely fast operating peripheral equipment such as disk storage systems and printers.
The most efficient use of such a system is realized when the various interconnected components of the system can communicate asynchronously, whereby the fast operating equipment need not communicate with, for example, a printer, at the printer's slower communication rate.
It is a well-known practice to employ memories as intermediate buffers between the components of a system for storing data written therein by the transmitting equipment at one speed, and read therefrom by destination equipment at another speed. With this arrangement, it is imperative that memory storage space is available when the transmitting equipment transmits data. Moreover, when the memory storage space is full, it is necessary that the transmitting equipment is signaled so that further transmission cannot be accomplished. It is equally important that the destination equipment be signaled by the intermediate buffer when the memory storage is empty so that further reading thereof cannot be accomplished until additional data has been written therein by the transmitting equipment.
It is not uncommon, therefore, to find memory structures for buffering asynchronous communications between digital machines. It is well-known that shift registers may be employed for serially writing digital words therein at a desired speed, and read serially therefrom at a different speed. The problem with this type of buffer, however, is that the data written therein must be rippled through every memory location until the data is available at the output end. With this technique, a substantial delay in time must be experienced in progressively shifting the data from the input of the shift register to its output.
More recently, buffer random access memories have been developed which take on a First In First Out (FIFO) characteristic. However, the movement of the data within such a memory is managed by a control section which maintains an account of which storage cells hold effective data. See, for example, U.S. Pat. Nos. 4,151,6608 and 4,459,681. These FIFO memory devices yet require the data to be shifted from cell to cell, and thus have inherently long through-put or fall-through times.
A further improvement in memory buffers is disclosed at Page 181 in the June, 1983 issue of Computer Design, wherein there is disclosed an input data bus to each storage location, and an output data bus onto which the data stored in any of the word locations can be read. With this system, however, memory write cycles are initiated on one edge of a write pulse, but data is actually written into the memory on the other transition thereof. The reliability of data written into the memory with this technique is generally good; however, data which is changing near the write pulse transition is unreliable. Moreover, the FIFO memory requires a running account of the particular addresses currently being written and read to determine the empty or full status of the buffer. Because various events may occur, both externally and internally within the FIFO memory, between the rising and falling transition of the write pulses, the true empty or full status frequently becomes uncertain. Therefore, the empty or full status cannot be absolutely guaranteed.
There is therefore a need for a FIFO memory buffer which has very nearly a zero through-put time, i.e., a zero fall-through time, and in which the empty or full status thereof can be determined with absolute certainty.
There is also a need for a FIFO type of memory buffer wherein all internal operations are commenced and carried through as a result of a single transition of a read or write signal.
A concomitant need exists for an extremely fast FIFO memory buffer wherein different memory words can be read and written simultaneously, or where the same word can be written and read within an extremely short period of time.